ECE 412Computer ArchitectureLecture #4

Table of Contents

ECE 412Computer ArchitectureLecture #4

Instruction Buffers

Current Topology for Decoding Instructions

CISC Problem #1:Variable Instruction Format (VIF)

Motivations for VIF: Motivation 1

Motivations for VIF: Motivation 1(continued)

Motivations for VIF: Motivation 2

Motivations for VIF: Motivation 3

Consequence of VIF:Sequential Decoding Problem

Decoding Alternatives

Decoding Alternatives (continued)

Performance and Decoding Options

Decoder Layouts

Pre Decode Cache with Fewer Decode Stages (AMD K5)