This work is supported under MARCO FCRP/GSRC with additional funding provided by Mentor Graphics® and Xilinx®

Soft Systems at the University of Illinois

Future system-on-a-chip designs will provide substrates that incorporate arrays of general-purpose microprocessors, application-specific instruction processors (ASIPs), and on-chip reconfigurable fabrics. The problem of orchestrating the mapping complex application software and system specifications onto such heterogeneous multi-processor substrates, while satisfying developer productivity, application efficiency and system reliability requirements, will be addressed in three complementary approaches. The first approach pushes the envelope of traditional high-level language programming models, allowing developers to continue to utilize their current skills and productive practices. The viability of this paradigm requires revolutionary analysis techniques, capable of providing a radically improved level of performance and reliability in increasingly irregular hardware environments. The second approach maps to application-specific processors from domain-specific (e.g. networking and wireless communication) application environments that break away from the sequential programming model. The third approach maps from similar domain-specific programming environments onto reconfigurable fabrics. It is our contention that all three approaches will be crucial for successful embedded system design in the next decade. These approaches together aim to bridge the application development concerns of programmer productivity, software reusability, and end-product functionality with implementation-cost concerns of speed, power efficiency, reliability and manufacturability. Underlying each of these efforts is the development of a deep static and dynamic analysis infrastructure capable of extracting and managing derived information on computation, control logic, memory accesses, data structures, and safety. This thrust will demonstrate programming environments that support software development for systems that incorporate the three significant on-chip structures named above. The environments will show special attention to program efficiency and correctness. The value of the underlying deep program analysis in improving program efficiency will also be demonstrated.

The faculty of the Soft Systems theme includes Andre DeHon (California Institute of Technology), Jose-Ignacio Navarro (Universitat Politecnica de Catalunya), and Vikram Adve, Steve Lumetta (University of Illinois), with Kurt Keutzer (University of California at Berkeley) and Wen-mei Hwu as Co-Theme Leaders