OVERVIEW

The standard design flow for the Linux-based Virtex Pro is to utilize the Xilinx Embedded Development Kit (EDK) for hardware entry, perform external command line compilation of an open-source Linux kernel which is brought back in to the tool, then eventual download and debug within EDK of the combined bitfile and elf. Presence of some external software is implicit in running the tools, for example Adobe Acrobat for documentation and the capability for unzipping files.

Setting up the proper design flow is a three-step process:

1. Creation of a suitable environment with compatible hardware and facilities (including OS issues).
2. Installation the required Xilinx ISE toolset and libraries.
3. Installation the primary EDK tool and additional IP libraries.

CAD TOOL ENVIRONMENT

ISE and EDK are supported under a number of platforms, but choosing preferred workstation hardware for the toolchain can ease problems later.

Environment issues to consider:

• Windows is the most stable for entry.
  

  Historically, the FPGA industry has been driven by small design teams, typically one individual. Inexpensive PC hardware was the sole possibility until fairly recently, and the tools are generally released earlier for Windows than Unix. Some features are only available within the PC environment: schematic capture and automatic simulation vector generation, for example.

• Cross compilation of kernels requires Linux
  

  Cross compiling kernels under Windows is reportedly nearly impossible, and fairly difficult on most Unix platforms. Keep in mind that "cross compile" in this context is anything but the target PowerPC which is distinctly different from an Apple PowerPC. The strongly favored environment is Red Hat Linux 7.3 or newer (support is moving toward Red Hat Enterprise).

• IMPACT download tool only recently available outside Windows
  

  With the release of ISE 6.2, downloading with Linux became possible, but is not completely problem-free. The IMPACT tool is marginal, although command line JTAG access is possible.

• Licensing is required under Linux
  

  The Xilinx tools, for reasons of economy, utilize an internal licensing scheme. Most other commercial CAD tools incorporate FLEXlm license management. Thus, while there is no problem with the Xilinx tools per se, external products which are required (Mentor Graphics ModelSim) or desired (Synplicity Synthesis) necessitate some license functionality.

• Larger design efforts require teams
  

  The larger FPGA parts available are sufficiently complex to require a team effort for design. This means version synchronization is necessary of tools like ISE among designers, and especially, synchronization of library part releases. Because Linux is more amenable to file sharing and central file service, only one version of an executable or library is visible to all users at any given time.

• Large Virtex Pro parts require significant compile times
  

  Unlike earlier generations, the newer FPGA parts require substantial compute resources to synthesize, place, and route. Compile times easily exceed hours in duration. The tools are significantly faster under Linux than Windows, somewhere between 20% and 40%.

Operating System Choice

Taken together, these factors tend toward a Red Hat Linux design environment. The cross compilation of Linux is the dominant factor, with the IMPACT download issue a close second. Locally we have established an environment where we can perform each task on a separate machine, but having hardware and software compiles co-existing on one machine is seen as desireable. The downloads are currently managed by a isolated bench host machine, which although cleanly runs the download tool, hampers JTAG debugging.

Xilinx has extensive support on their website for problems. Often the first stop for issue resolution is to search the Answers Database. Record Numbers 8097 and 18612 deal with download possiblities for Linux. Although Red Hat 7.3 and 8.0 are theorically supported, the actual kernel you have may require compilation of the parallel port drivers. Red Hat 9.0 indicates only partial support, but the improvement over 7.3 makes this the primary choice for this work. The remainder of this installation is based upon a Red Hat 9.0 selection. [We are evaluating a transition to Red Hat Enterprise in the very near future.]

There is a wealth of data on the Xilinx website, but locating what you need is not always easy. Obtaining and using a MySupport account is worthwhile.

Hardware Choice

Two general setups are possible: design entry, synthesis, and PAR on a Windows platform, which is also sharing files with a companion Linux machine designated for kernel builds. Downloads can be performed either by the first machine, or for convienence, a third dedicated benchtop Windows host. This is our current setup at the Soft Systems Lab. It is slightly awkward to export the Linux build information to the kernel compiler, and designing and downloading are single-user tasks, that is, only one individual has the desktop (console or exported) at a time.

Another setup, which is currently under evaluation, is to run the Xilinx entry and synthesis tools on the same machine as the kernel builds; this implies ISE/EDK full functionality under Linux. Downloads can either be by this machine or the bench host machine. Because this is the perferred environment from Xilinx, the rest of this installation is for a single-machine with combined HW and SW compilation approach. [Locally not yet in place; we use Windows XP and Red Hat 9.0 while Enterprise is being brought online.]

Dedicate a reasonable performance machine to this work. Currently, I use a dual AMD Athlon MP 2200+ with 1.0 GB RAM, which should be considered a minimum capability platform. Synthesis and compiles take about 45 minutes each, and memory usage ranges from 700 to 900 MB for a full V2P7 or partial V2P30 design.

Next, ISE installation...