OVERVIEW

This document is designed to provide a initial walk-through of a basic Linux design on the Xilinx ML310. The first part is creation of a hardware build for and existing kernel, and the second part compiles a kernel for existing hardware and downloads by two methods.

It is assumed the user has already performed an ISE and EDK installation, a cross compile installation, and completed the EDK Tutorial material, but by way of review, a short synopsis of the tool view is presented.

Recall the left-most white window contains a listing of the files and IP present in the project. The items are summarized roughly in the microprocessor hardware specification file (system.mhs) and microprocessor software specification (system.mss) files respectively. These two main files are edited and modified using "Project>Add/Edit Cores..." and "Project>Software Platform Settings..." dialog tools. Recall also that various activities are initiated using the "Tools" pulldown on the taskbar, and proceed generally down the list presented. Results, warnings, and errors are displayed in the lower panel.

It is possible, and occasionally useful, to manually configure the MHS and MSS files. EDK will automatically synchronize both files when using the above dialogs, but difficulties can arise if edited by external means; use caution in doing this. Viewing a project block diagram (and some manipulation) can be performed by "Project>View Block Diagram", but be aware that a similar synchronization is performed whenever this happens as well.

JumpStart Sequence

As mentioned earlier, the fastest approach is a three-step process: first, learn the overall tool flow with a basic design, next, learn something about Virtex Pro platform design and advanced techninques such as exporting/importing to ISE, and finally, perform this ML310 board-specific build and download.

1. After first obtaining and setting up ISE, EDK, and the cross compile environment, and after having performed the Xilinx built-in tutorials, then create a clean workspace and download the project files and start EDK:
   • Into the new workspace, copy the Xilinx ML310 PCI design in and unzip.

     In the next step, notice that EDK will initially locate itself in the last directory worked; it is prudent to select Look in: to confirm the correct location as the default files and directories have common names regardless of the project designation. This hint also applies to other tools, for example, importing or exporting files to ISE, etc.

   • Start XPS, and using File>Open Project navigate to the ml310_pci_design, and select ml310_pci_linux.xmp.

     This design is a complete project with a hardware pre-compiled bit file and a compiled kernel (in implementation/ml300_pci_bootloop.bit and with manual creation of ppc405_0/default/zImage.elf respectively). It is technically feasible to create a systemACE file with the downloaded components and boot the kernel. In fact, a prebuilt ml310_pci_linux.ace file is already present as well, which could be copied to the microdrive for immediate usage as a sanity check or troubleshooting step.

2. In order to regenerate the hardware design, it is first necessary to delete the existing results. From the toolbar, select Tools>Clean>All. As more experience is gained, which files can be selectively deleted will become apparent. It is always safe, albeit time consuming, to remove all files and start cleanly.

3. Each step in the Tools pulldown corresponds to a necessary action, and selecting a lower item will cause any prerequisite actions to be initiated. For illustration, individual tasks are separately performed below.

   • Select Tools>Generate Libraries and BSPs. This examines the specification files and configures appropriate paramter widths, investigates for possible memory overlap, checks the license status of various IP parts as well as operational status, and finally assembles a board support package or BSP, which is a directory tree of correct drivers, parameters, etc. required for the kernel build.

     It is tempting to omit this step when not actually compiling a kernel, but because of the checking performed, it is nearly always valuable. The following listing "Build All User Applications" is specific to code for standalone systems and can be safely skipped. Likewise, "Get Program Size" is aimed at strictly-budgeted embedded projects and will also be omitted for our Linux work.

   • Select Tools>Generate Netlist in order to prepare and initiate synthesis. This step is fairly time consuming, taking about 20 minutes on a 2 GHz processor.

   • Select Tools>Generate Bitstream to invoke PAR. This step generally takes approximately the same amount of time as the synthesis step, but can take significantly longer if cases of high utilization.

     At this point, the design has been synthesized, placed, and routed. In the earlier tutorials, the possibility of exporting to ISE for these steps was illustrated. Under most circumstances, using the above procedure is preferred as optimal flags are already set by various scripts interacting with XST and ngdbuild. The final requirement is to incorporate some necessary BRAM initialization. As it happens, the PPC processor comes out of reset relatively quickly, and will need a small piece of assembly code to initiate a tight loop prior to being exposed to the kernel startup procedure. Xilinx calls this bootloop, and terms inclusion of the initialization process "updating the bitstream".

   • Select Tools>Update Bitstream to incorporate the instructions within the bit file, which is a fairly rapid procedure.

   The hardware compilation should now be complete. Next, the FPGA configuration file will be merged with the existing compressed kernel elf and assembled into a single top.ace file, which in turn will be copied onto the demo microdrive for booting. This will be accomplished from a command line invocation of the Xilinx Microprocessor Debugger, or XMD. A number of steps are embodied in the script which produces the top.ace file, for example, the iMPACT software download utility is run in non-graphical form. Because of this interaction, it should be remembered that most tools are being started with EDK-specific .ini parameters.

   For future projects, remember to copy over these setup files, or reproduce their behavior with a new file.

4. Select Tools>Xygwin Shell which will open a window and type pwd to confirm you are in the same directory /ml310_pci_design. This directory will contain the system_linux.xmp file, and running the scripts from here will ensure the proper initialization files are utilized.
   • You will need to locate the existing Linux image where it can be located for inclusion in the ace file, or if compiled locally, that file. For this project, Xilinx has included a script in the data directory which expects specific locations and filenames. You will create a default directory and copy the zImage.elf there, and rename the results of the Update Bitstream to match the expected script version name (in future tutorials, default names will be used).

   • Download, save, and unzip the Xilinx kernel ml310_pci_linux_bit_elf_ace.zip to a to a temporary location.

   • Type the following commands in the Xygwin shell:
     

     mkdir ppc405_0/default

     cp (temporary_dir)/zImage.elf ppc405_0/default

     cp implementation/download.bit implementation/ml310_pci_bootloop.bit

   • And, finally, move to the data directory and execute the batch file:

     cd data

     ./genace_pci_linux.bat

     Summary of the various commands:
     

     • xmd starts the Xilinx Microprocessor debugger and runs the genace TCL script.
     • -jprog option configures via JTAG
     • -board is specified as ML310 so genace script can locate the devices in the chain
     • -hw is location of bitstream configuration
     • -elf is location of compiled kernel
     • -ace is the output ace file name

   Linux will need a root filesystem to operate. This tutorial will initially utilize the rootfs shipping on the demo microdrive. Later tutorials will create this anew from scratch. Also, the Xilinx boot screen allowing selection of the proper kernel to boot will be retained. The following steps insert the ml310_pci_linux.ace into the existing microdrive arrangement.

5. If the local machine has a compact flash slot, the microdrive can be inserted directly. If not, the ml310_pci_linux.ace file must be transfered to a location where that can be accomplished, either to a USB CF device, or most likely a laptop with PCMCIA capability (for the supplied adapter).

6. On the microdrive, copy the iml310_pci_linux.ace to the directory XILINX/cfg5. The last three configuration directories are intended for user files, and are menu items A, B, and C respectively.

   A more common name is top.ace, but the loader will accept any file with the .ace suffix.

7. Insert the updated microdrive into the CF slot on the ML310 and power on the board. On the boot screen, select User Configuration A to boot. You should see the OS uncompressing and booting on the serial terminal. At the login prompt, type root and the default password 310ml.

   To avoid corrupting the microdrive, the system should always be halted by logging as root, opening an Xterm, and typing telinit 0 .

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This kernel has pre-configured framebuffer support for a Matrox Millenium I or II PCI video card. If such a card (and only this card) is detected on the PCI bus, X11 can be started by the next steps.

1. During bootup on the second (PCI) display the Tux Penguin will appear in the upper left corner, indicating VGA is present.

2. After loggin in, configure the framebuffer for a higher resolution: fbset 1024x768-70

3. Start the X session by typing startx &, and the second display should show FVWM.

   There is a minor problem with screenblank with this card, so in an xterm on the second display, type xset s noblank.

Next, ML310 Part 2: Building and Downloading a Linux Kernel