Run-time Adaptive Cache Management (PostScript version, PDF version)
Teresa L. Johnson, Daniel A. Connors, and Wen-mei W. Hwu
Proceedings of the 31st Annual Hawaii International Conference on system Sciences, Wailea,
Hawaii, Jan. 5-8, 1998
As memory latencies increase, the importance of cache performance
improvements at each level of the memory hierarchy will continue to grow.
Also, as the available chip area grows,
it makes sense to spend more resources to allow intelligent control over the
cache management, in order to adapt the caching decisions to the dynamic
accessing behavior.
In the past, cache management techniques such as cache bypassing
were implemented manually at the instruction programming level.
Additionally, spatial locality was often exploited
via large block sizes and other fixed amounts of hardware prefetching.
Our goal is to develop a framework for adaptive and automatic control of
cache management techniques.
The objective of our research is to improve cache effectiveness
in order to deal with long memory latencies, utilizing run-time
adaptive cache management techniques, optimizing both performance
and cost of implementation. Specifically, we are aiming to increase
data cache effectiveness for integer programs. We propose
a microarchitecture scheme where the hardware determines data
placement based on dynamic referencing behavior.
This scheme is fully compatible with existing Instruction Set Architectures.
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