Comparing Software and Hardware Schemes For Reducing the Cost of Branches(PostScript version, PDF version)
Wen-mei W. Hwu, Thomas M. Conte, and Pohua Chang
Proceedings of the 16th Annual International Symposium on Computer Architecture, Jerusalem, Israel, May 28- June 1, 1989, pp. 224-233.
Pipelining has become a common technique to increase
throughput of the instruction fetch, instruction decode,
and instruction execution portions of modern computers.
Branch instructions disrupt the flow of instructions
through the pipeline, increasing the overall execution
cost of branch instructions. Three schemes to reduce
the cost of branches are presented in the context of a
general pipeline model. Ten realistic Unix domain
programs are used to directly compare the cost and per-
formance of the three schemes and the results are in
favor of the software-based scheme. For example, the
software-based scheme has a cost of 1.65 cycles/branch
vs. a cost of 1.68 cycles/branch of the best hardware
scheme for a highly pipelined processor (11-stage
pipeline). The results are 1.19 (software scheme) vs.
1.23 cycles/branch (best hardware scheme) fro a moderately
pipelined processor (5-stage pipeline).
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