IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors (PostScript version, PDF version)
Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Water, and Wen-mei W. Hwu
Proceedings of the 18th Annual Int'l Symposium on Computer Architecture, Toronto, Canada, May 28, 1991, pp. 266-275

The performance of multiple-instruction-issue processors can be severely limited by the compiler's ability to generate efficient code for concurrent hardware. In the IMPACT project, we have developed IMPACT-I, a highly optimizing C compiler to exploit instruction level concurrency. The optimization capabilities of the IMPACT-I C compiler are summarized in this paper. Using the IMPACT-I C compiler, we ran experiments to analyze the performance of multiple-instruction-issue processors executing some important non-numerical programs. The multiple- instruction-issue processors achieve solid speedup over high-performance single-instruction-issue processors.

We ran experiments to characterize the following archi- tectural design issues: code scheduling model, instruction issue rate, memory load latency, and function unit resource limitations. Based on the experimental results, we propose the IMPACT architectural framework, a set of architectural features that best support the IMPACT-I C compiler to generate efficient code for multiple-instruction-issue processors. By supporting these architectural features, multiple-instruction- issue implementations of existing and new architectures receive immediate compilation support from the IMPACT-I C compiler.

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