Home
Home/Mobile: (217) 840-9355 |
ERIK NYSTROM
FALL 2004 enystrom@uiuc.edu |
Office
223 CSL MC-228 Voice: (217) 333-4171 Fax: (217) 333-5579 |
OBJECTIVE
To seek a tenure track faculty position or a position
in an industrial research lab.
The diverse nature of
compilation objectives frequently pits the containment of compilation time
against the need for additional analysis precision. However, there is a very
complex relationship between the two of which neither the programmer nor the
compiler are typically aware. The core of my interest is developing algorithms
that attempt to provide a maximal amount of precision for a given budget of
time. This has a two-fold importance.
First, the structure of a program influences analysis algorithms where,
for two identically sized programs, one may be extremely expensive to analyze
and produces little useful results while the other finishes quickly and yields very
precise results. Second, the use of more precise and expensive algorithms can
actually yield better results in less time. Analysis algorithms must be
constructed to start strong and intelligently degenerate on the fly. Finally,
analysis (in reality) is not done in a vacuum. The results of previous analysis
runs should be used to control the targeting of future runs while
simultaneously adjusting to the fact that some of the code base may have
changed. This is critical for large software systems. These goals require
flexible and robust analysis techniques to allow algorithmic adaptability as
well as prevent information loss through the use of rich representations.
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Nov.
2004 |
Ph.D. Elec. & Comp Engr. |
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GPA 4.00 |
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May
2002 |
M.S. Elec.
& Comp Engr. |
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GPA 4.00 |
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May
1998 |
B.S. Elec. & Comp Engr. |
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GPA 3.94 |
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Microprocessor
Research Labs |
Intel
Corp |
5/2000 - 8/2000 |
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IA32
Performance analysis |
Intel
Corp |
6/1999 - 8/1999 |
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IA32
Performance analysis |
Intel Corp |
6/1998 - 8/1998 |
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Embedded
Architecture Modeling and Analysis |
IBM |
2/1998 - 5/1998 |
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Co-instructor
for Engineering Design Course |
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9/1995 - 12/1997 |
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ASIC
Design, Behavioral Modeling, Debugging |
Nortel |
9/1994 - 5/1996 |
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Research
Assistant |
Wen-mei Hwu |
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9/1998 - Present |
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Research
Assistant |
Alexandre Eichenberger |
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5/1997 - 8/1997 |
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Independent
Study |
Tom
Conte |
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1/1997 - 5/1997 |
2002
– 2004 Pointer analysis (TR03, TR04, PASTE, SAS, Dissertation)
The
increasing complexity of applications, in combination with greater demand for
performance in the face of power inefficient, long latency memory accesses, has
increased the importance of a compiler’s clarity of view with respect to an
application’s actual memory activity.
However, the quality of the information obtained is often poor because
the cost of performing very accurate pointer analysis can be substantial. This
work takes the approach that pointer analysis algorithms can attain high
accuracy across the bulk of a program while maintaining reasonable, if not
fast, run times because: 1) Improving
accuracy can benefit efficiency 2) Fine-grained, localized control over
accuracy enables the analysis process to avoid many costly situations. While still in progress, this work has
yielded an efficient, flexible, and accurate context-sensitive, field
sensitive, and heap sensitive algorithm based on Andersen’s formulation of
points-to relationships.
The
following summarize three interesting results from this research. 1) The
framework can complete both call graph discovery and full program pointer
analysis in a few seconds for the bulk of SPEC and always in a few minutes.
This is a substantial improvement when compared to similar frameworks that
required many hours if not days. 2) The framework uses a more safe form of field
sensitivity, more accurate form of context-sensitivity, and an
efficient/accurate form of heap object specialization to aid both the
usefulness and safety of the results. 3) The net effect has allowed the
analysis system, in some instances, to remove over 90% of the perceived
accesses to program objects. The pointer analysis framework is not just a
theoretical model, but has been implemented within the IMPACT compiler
framework and is currently under test for controlling everything from
scheduling to custom object allocation into low-power SRAMs.
2001
– 2003 Post-link optimization and EPIC pipeline design (MICRO)
The
central idea for this work is the use of dynamically derived information to
modify code apostori. Investigations have targeted
both the guiding of the compiler using programs phases instead of profile
weights as well as pipeline design to tolerate stalls the compile was unable to
anticipate.
2000
– 2004 IA64 compiler framework (Hotchips,
Mp Forum)
This
work focuses on demonstrating the full performance potential of the implemented
IA64 processor family. IA64 is reliant on a compiler to generate code that can
efficiently execute on the processor. For this reason, developing a good
compiler infrastructure is paramount in getting good application performance.
2000
– 2002 Speculation support for Runtime Optimization (PACT, Masters Thesis)
A
major hurdle in dynamic optimization is the preservation of precise exceptions
while not constraining optimization. This work establishes a method through which
freedom can be given to both software and hardware dynamic optimization systems
while fully preserving the machine state at any exception.
2000
– Memory Access Patterns (ISCA MPF Workshop)
Using
resources during an internship at Intel, this work sought to characterize the
memory access patterns of various benchmarks with the objective of using the
results to guiding prefetching mechanisms.
1999 – 2001 Dynamic
Optimization via Hot Spots
(ISCA, TOC)
A hot spot is a region of
code that is heavily executed over an interval of time. This work focused on
the use of detected hotspots as a guide for the formation of traces suitable
for both improving fetch performance and for enabling future performance driven
dynamic optimizations.
1997
– 1998 Modulo Scheduling for a clustered processor
architectures (MICRO)
Modulo
scheduling is a software pipelining technique in which
an iteration of a loop is scheduled to start at a regular, constant interval.
This allows for a predictable overlap of the execution of multiple iterations.
The process of obtaining an efficient schedule is complicated by the presence
of a clustered architecture where access times to registers vary based on the
location of the register within the separate registers files.
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Bottom-up and Top-down Context-Sensitive
Summary-based Pointer Analysis E. Nystrom, H.-S. Kim, W. Hwu, To appear in the proceedings of the 11th Static Analysis Symposium, August 2004. |
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Importance of Heap Specialization in Pointer
Analysis E. Nystrom, H.-S. Kim, W. Hwu, |
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Field-testing IMPACT EPIC research results in
Itanium 2 J. Sias, S. Ueng, G. Kent, The 31st Annual IEEE/ACM International Symposium on
Computer Architecture, June 2004. |
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Scalable, precise context-sensitive top-down
process for modular points-to analysis E. Nystrom, H. Kim, W. Hwu, |
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Compaction algorithm for precise modular
context-sensitive pointer analysis |
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Beating in-order stalls with "flea-flicker"
two-pass pipelining |
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Architectural Support for Persistent, Dynamic
Code Transformations Master's Thesis, Department of Electrical and
Computer Engineering, |
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Vacuum Packing:Extracting Hardware-Detected Program Phases for
Post-link Optimization |
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Itanium
Performance Insights Presentation
at Microprocessor Forum, October 2001. |
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Itanium Performance Insights from the IMPACT/iA64 Compiler J. Sias, M. Merten, E. Nystrom, R. Barnes, J. Matarazzo, C. Shannon, W. Hwu, Hotchips, August 2001. |
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Characterization of Repeatable Data Access
Patterns in Integer Benchmarks E.
Nystrom, R. Ju, and W. Hwu, Workshop
on Memory Performance Issues, 28th
IEEE/ACM International Symposium on Computer Architecture, July 2001. |
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Code
Reordering and Speculation Support for Dynamic Optimization E.
Nystrom, R. Barnes, M. Merten, and W. Hwu, Int'l
Conference on Parallel Architectures and Compilation Tech., September 2001. |
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An
Architectural Framework for Run-Time Optimization M. Merten, A. Trick, R. Barnes, E. Nystrom,
C. George, J. Gyllenhaal, and
Wen-mei W. Hwu, IEEE
Transactions on Computers, Vol. 50, No. 6, June 2001, pp. 567-589. |
A Hardware Mechanism for Dynamic Extraction and Relayout of Program Hot SpotsM.
Merten, A. Trick, Proceedings of the 27th
IEEE/ACM International Symposium on Computer Architecture, 2000. |
Effective Cluster Assignment for Modulo SchedulingE.
Nystrom, A. Eichenberger, Proceedings of the 31st
IEEE/ACM International Symposium on Micro-Architecture, 1998. |
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1999,
Computers and Digital Techniques |
1999,
32nd Intern. Symposium on Microarchitecture
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1999, Intern. Conference on Supercomputing |
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2000,
Conf. on Prog.
Language Design and Implementation |
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2002,
35th Intern. Symposium on Microarchitecture |
2002,
Int'l Conf. on Parallel Architectures and Compilation Tech |
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2002,
Int'l Symposium on Code Generation and Optimization |
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2003,
International Symposium on Computer
Architecture |
2003,
Int'l Symposium on Code Generation and Optimization |
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2003,
Compilers, Arch., and Synthesis for
Embedded Systems |
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2004,
International Symposium on Computer
Architecture |
2004,
37th Intern. Symposium on Microarchitecture |
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GSRC,
C2S2 |
2002,
2003 |
Aided
in the composition of the research object and research plan of the soft
systems theme for the GSRC re-proposal; Participated in GSRC, C2S2 annual
reviews and quarterly meetings |
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GSRC Theme Meeting |
12/03 |
15min position statement,
20 min topical overview; compiler analysis and verification |
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GSRC Review |
09/03 |
2hr poster session for
topical overview of scalable pointer analysis |
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GSRC Preliminary meeting |
03/03 |
45min, presentation for
software systems research overview |
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C2S2 Annual review |
03/03 |
2hr poster session on
compiler analysis and operating systems |
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PACT |
09/01 |
30min, Conference talk for
PACT 2001 |
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Microsoft |
05/01 |
30min, Interview talk on
speculation support |
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Intel |
09/00 |
30min, Internship summary
on memory access pattern characterization |
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Intel |
09/98 |
30min, Internship summary
on memory coherence and hyper-threading |
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MICRO |
12/98 |
30min, Conference talk for
MICRO 1998 |
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Intel
Doctoral Fellowship |
National
Science Foundation Graduate Fellowship |
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National
Goldwater Scholarship |
Lockheed-Martin
Undergraduate Scholarship |
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Phi
Kappa Phi |
Golden
Key Honor Society |
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IEEE
and ACM member |
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ECE442, 412,
CS433 |
Design
of a parallel computer systems, distributed a workloads, and fault tolerance
and reliability |
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ECE 452,
382, 362, 344 |
Numerical circuit
analysis, VLSI, logic, and fabrication |
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CS
326, 373, 375 |
Front-end compilation,
algorithms, and automata theory |
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ECE 411, 497 |
Graduate architecture and
compiler course along with a special topics course discussing current
research and emerging technologies |
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GE 497 |
Business and technology |
REFERENCES
|
Wen-mei Hwu |
Professor UIUC |
217-244-8270 |
215 Computer Systems
Laboratory |
|
Thomas Conte |
Professor NCSU |
919-515-5067 |
Department
of Elec. and Comp Engr. |
|
Roy Ju |
IA-64 Compiler Research, Intel |
408-765-8401 |
Microprocessor
Research Lab Intel Corp., MS SC12-303 |
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Alexandre Eichenberger |
Exploratory System Arch., IBM TJ Watson |
(914) 945-1812 |
Exploratory System
Architecture Room 27-245 |
|
Nacho Navarro |
Assoc. Prof. UPC |
+34 934016989 |
Computer Architecture Dept. Universitat Politecnica de Catalunya Jordi Girona 3, Modul 6 |
|
Steven Lumetta |
Assistant Prof. UIUC |
(217) 244-5564 |
209 Computer Systems
Laboratory 130 |