HyperLink   Scalar Program Performance on Multiple-Instruction-Issue Processors with a Limited Number of Registers.
Publication Year:
  Scott A. Mahlke, William Y. Chen, Pohua P. Chang, Wen-mei Hwu
  Proceedings of the 25th Annual Hawaii Int'l Conference on System Sciences, pp. 34-44, Jan. 6-9, 1992

In this paper the performance of multiple-instruction- issue processors with variable register file sizes is examined for a set of scalar programs. We make several important observations. First, multiple-instruction-issue processors can perform effectively without a large number of registers. In fact, the register files of many existing architectures (16-32 registers) are capable of sustaining a high instruction execution rate. Second, even for small files (8-12 registers), substantial performance gains can be obtained by increasing the issue rate of a processor. In general, the percentage increase in performance achieved by increasing the issue rate is relatively constant for all register file sizes. Finally, code transformations designed for multiple-instruction-issue processors are found to be effective for all register sizes; however, for small register files, the performance improvement is limited due to the excessive spill code introduced by the transformation.