HyperLink   Critical issues regarding HPS, a high performance microarchitecture
Publication Year:
  Yale N. Patt, Stephen W. Melvin, Wen-mei Hwu, Michael Shebanow
  Proceeding MICRO 18 Proceedings of the 18th annual workshop on Microprogramming, 1985

HPS is a new model for a high performance microarchitecture which is targeted for implementing very dissimilar ISP architectures. It derives its performance from executing the operations within a restricted window of a program out-of-order, asynchronously, and concurrently whenever possible. Before the model can be reduced to an effective working implementation of a particular target architecture, several issues need to be resolved. This paper discusses these issues, both in general and in the context of architectures with specific characteristics.