A machine description facility allows compiler writers to
specify machine execution constraints to the optimization
and scheduling phases of an instruction-level parallelism
(ILP) optimizing compiler. The machine description (MDES)
facility should support quick development and easy
maintenance of machine execution constraint descriptions by
compiler writers. However, the facility should also allow
compact representation and efficient usage of the MDES
during compilation. This paper advocates a model that
allows compiler writers to develop the MDES in a high-level
language, which is then translated into a low-level
representation for efficient use by the compiler. The
discrepancy between the requirements of the high-level
language and the low-level representation is reconciled with
a collection of transformations that derive efficient low-level
representations from the easy-to-understand high-level
descriptions. In order to support these transformations, a
novel approach to representing machine execution constraints
has been developed. Detailed and precise descriptions of
the execution constraints for the HP PA7100, Intel Pentium,
Sun SuperSPARC, and AMD-K5 processors are analyzed to show
the advantage of using this new representation. The results
show that performing these transformations and utilizing the
new representation allow easy-to-maintain detailed
descriptions written in high-level languages to be
efficiently used by ILP-optimizing compilers.