Our recent work in microarchitecture has identified a new model of
execution, restricted data flow, in which data flow techniques are used
to coordinate out-of-order execution of sequential instruction streams.
We believe that the restricted data flow model has great potential for
implementing very high performance computing engines. This paper defines
a minimal functionality variant of our model, which we are calling
HPSm. The instruction set, data path, timing and control of HPSm are all
described. A simulator for HPSm has been written, and some of the
Berkeley RISC benchmarks have been executed on the simulator. We report
the measurements obtained from these benchmarks, along with the
measurements obtained for the Berkeley RISC II. The results are
encouraging.