With the advent of several accurate and sophisticated statistical algorithms and pipelines for DNA sequence analysis, it is becoming increasingly possible to translate raw sequencing data into biologically meaningful information for further clinical  analysis  and  processing.   However,  given  the  large volume of the data involved,  even modestly complex algorithms would require a prohibitively long time to complete. Hence it is the need of the hour to explore non-conventional implementation platforms to accelerate  genomics research. In this work, we present an FPGA-accelerated implementation of the Pair HMM forward algorithm, the performance bottleneck in the HaplotypeCaller, a critical function in the popular GATK variant calling tool.  We introduce the PE ring structure which, thanks to the fine-grained parallelism allowed  by  the  FPGA,  can  be  built  into  various  configurations striking a trade-off between instruction-level parallelism  (ILP)  and  data  parallelism.   We  investigate  the  resource  utilization  and performance  of  different  configurations.  Our solution can achieve a speed-up of up to 487× compared to the C++ baseline implementation on CPU and 1.56× compared to the best published hardware implementation.

@inproceedings{Huang:2017:HAP:3020078.3021749,
author = {Huang, Sitao and Manikandan, Gowthami Jayashri and Ramachandran, Anand and Rupnow, Kyle and Hwu, Wen-mei W. and Chen, Deming},
title = {Hardware Acceleration of the Pair-HMM Algorithm for DNA Variant Calling},
booktitle = {Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},
series = {FPGA '17},
year = {2017},
isbn = {978-1-4503-4354-1},
location = {Monterey, California, USA},
pages = {275--284},
numpages = {10},
url = {http://doi.acm.org/10.1145/3020078.3021749},
doi = {10.1145/3020078.3021749},
acmid = {3021749},
publisher = {ACM},
address = {New York, NY, USA},
keywords = {FPGA, PE ring, computational genomics, forward algorithm, hardware acceleration, pair-HMM},
}