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All compilers that support multiple target processors will typically use an intermediate representation to denote the converted or optimized code. One of the important aspects of this intermediate representation is that it provides the exibility of generating code for a nonexistent architecture, i.e., research architectures with no hardware support. To support an architecture, a code generator is required to convert the intermediate representation to assembly language for a target processor. This invariably means that in order to test a research (or experimental) architecture, a code generator must exist for the development platform being used. This platform-specific requirement can be quite constraining for investigating new architectural features because some of the established conventions of an architecture only reside within the internal documents of the architecture's manufacturer.
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