|
|
Superscalar and very long instruction word (VLIW) processors provide significant performance improvements over scalar processors by simultaneously executing multiple instructions. The effectiveness of these processors depends on the ability of compilers to provide sufficient instruction-level parallelism (ILP) in program code. However, recent studies show that conventional code optimization and scheduling methods cannot provide enough ILP to obtain a sustained speedup of more than two for nonnumeric programs [1],[2],[3]. The high frequency of conditional branch instructions in nonnumeric programs is mostly responsible for these poor results.
|