HyperLink   Matching On-Chip Data Storage To Telecommunication And Media Application Properties.
Publication Year:
  Hillery C. Hunter
  PhD thesis, Department of Electrical and Computer Engineering, University of Illinois, Urbana IL, 2004

This dissertation describes hardware and software necessary for compiler-controlled power savings in embedded data storage systems. Recent techniques for saving dynamic and static power in specialized SRAM arrays are leveraged to provide port, latency, and sleep configurability. Using advanced interprocedural pointer analysis to provide complete resolution of potential memory accesses, the compiler chooses a power-saving configuration for each program data object. Data objects are then grouped according to the number of needed ports and desired access latency.

Both the hardware and software design of configurable SRAM was driven by a data intent characterization of telecommunication and media applications. This characterization is described, along with description of its application to other methods for power savings in embedded systems.

For configurable SRAM, data storage savings in the range of 29% static power and 6% dynamic power are achieved without sacrificing code performance. When slight performance degradation can be tolerated, the compiler uses profile feedback to realize an average of 51.7% static and 9.4% dynamic power reduction.